TMS320DM642 datasheet(31/178 Pages) TI

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

GP0[15]/PRST(3)

General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I).

GP0 14 pin (I/O/Z) or PCI clock (I)

GP0[14]/PCLK(3)

GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z)

GP0[13]/PINTA(3)

GP0 12 pin (I/O/Z) or PCI bus grant (I)

GP0 11 pin (I/O/Z) or PCI bus request (O/Z)

GP0[12]/PGNT(3)

GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z)

GP0[11]/PREQ(3)

GP0 9 pin (I/O/Z) or PCI initialization device select (I)

I/O/Z

GP0[10]/PCBE3(3)

Note: By default, no function is enabled upon reset. To configure these pins, see

the Device Configuration section of this data sheet.

GP0[9]/PIDSEL(3)

GP0 3 pin (I/O/Z)

Boot Configuration: PCI EEPROM Auto-Initialization (EEAI).

GP0[3]

IPD

0 - PCI auto-initialization through EEPROM is disabled (default).

1 - PCI auto-initialization through EEPROM is enabled.

General-purpose 0 pin (GP0[0]) (I/O/Z) [default]

This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0]

(output only) pin or output as a general-purpose interrupt (GP0INT) signal

GP0[0]

I/O/Z

IPD

(output only).

Note: This pin must remain low during device reset.

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter

(VDAC) output [output only] [default] or this pin can be programmed as a GP0 8

pin (I/O/Z)

Boot Configuration: PCI frequency selection (PCI66).

If the PCI peripheral is enabled (PCI_EN pin = 1), then:

0 - PCI operates at 66 MHz (default).

VDAC/GP0[8]/PCI66(3)

AD1

I/O/Z

IPD

1 - PCI operates at 33 MHz.

The –500 device supports PCI at 33 MHz only. For proper –500 device operation

when the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up

with a 1-k

Ω resistor at device reset.

Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin be must not

pulled up.

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be

CLKOUT6/GP0[2](3)

I/O/Z

IPU

programmed as a GP0 2 pin (I/O/Z).

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be

CLKOUT4/GP0[1](3)

I/O/Z

IPU

programmed as a GP0 1 pin (I/O/Z).

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or EMAC

Boot Configuration: PCI enable pin (I)

The PCI_EN pin and the MAC_EN pin control the selection (enable/disable) of

PCI_EN

IPD

the HPI, EMAC, MDIO, and GP0[15:8], or PCI peripherals. The pins work in

conjunction to enable/disable these peripherals (for more details, see the Device

Configurations section of this data sheet).

HINT/PFRAME(3)

I/O/Z

Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)

Host control – selects between control, address, or data registers (I) [default] or

HCNTL1/PDEVSEL(3)

I/O/Z

PCI device select (I/O/Z).

Host control – selects between control, address, or data registers (I) [default] or

HCNTL0/PSTOP(3)

I/O/Z

PCI stop (I/O/Z)

Host half-word select – first or second half-word (not necessarily high or low

HHWIL/PTRDY(3)

I/O/Z

order)

[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)

HR/W/PCBE2(3)

I/O/Z

Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)

HAS/PPAR(3)

I/O/Z

Host address strobe (I) [default] or PCI parity (I/O/Z)

Host chip select (I) [default] or PCI parity error (I/O/Z)

HCS/PPERR(3)

I/O/Z

Host data strobe 1 (I) [default] or PCI system error (I/O/Z)

HDS1/PSERR(3)

I/O/Z

Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)

Note: If unused, the following HPI control signals should be externally pulled

HDS2/PCBE1(3)

I/O/Z

high.

HRDY/PIRDY(3)

I/O/Z

Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).

Device Overview

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