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TMS320DM642 Datasheet(PDF) 86 Page - Texas Instruments |
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TMS320DM642 Datasheet(HTML) 86 Page - Texas Instruments |
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86 / 178 page  www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Table 5-11. Switching Characteristics Over Recommended Operating Conditions During Reset (1) (2) (3) (see Figure 5-9) –500 –600 NO. PARAMETER UNIT –720 MIN MAX 2 td(RSTL-ECKI) Delay time, RESET low to AECLKIN synchronized internally 2E 3P + 20E ns 3 td(RSTH-ECKI) Delay time, RESET high to AECLKIN synchronized internally 2E 8P + 20E ns 4 td(RSTL-ECKO1HZ) Delay time, RESET low to AECLKOUT1 high impedance 2E ns 5 td(RSTH-ECKO1V) Delay time, RESET high to AECLKOUT1 valid 8P + 20E ns 6 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z high impedance 2E 3P + 4E ns 7 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z valid 16E 8P + 20E ns 8 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2E ns 9 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 8P + 20E ns 10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2E ns 11 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 8P + 20E ns 12 td(RSTL-LOWIV) Delay time, RESET low to low group invalid 0 ns 13 td(RSTH-LOWV) Delay time, RESET high to low group valid 11P ns 14 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 0 ns 15 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P 8P ns (1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. (2) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. (3) EMIF Z group consists of: AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO all of which apply only when PCI EEPROM is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the XSP_CLK/MDCLK and XSP_DO/MDIO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0, VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0, VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA, GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0]. DM642 Peripheral Information and Electrical Specifications 86 |
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