TMS320DM642 datasheet(26/178 Pages) TI

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VP0D[10]

VP0D[11]

VP0D[12]/ACLKR0

VP0D[13]/AFSR0

VP0D[14]/AHCLKR0

VP0D[15]/AMUTEIN0

VP0D[16]/AMUTE0

VP0D[17]/ACLKX0

VP0D[0]

VP0D[1]

VP0D[2]/CLKX0

VP0D[3]/FSX0

VP0D[4]/DX0

VP0D[5]/CLKS0

VP0D[6]/DR0

VP0D[7]/FSR0

VP0D[8]/CLKR0

VP0D[9]

VP0D[18]/AFSX0

VP0D[19]/AHCLKX0

Capture/Display

Buffer

(2560 Bytes)

VP0CLK0

VP0CLK1

VP0CTL0

VP0CTL1

VP0CTL2

Timing and

Control Logic

Video Port 0 (VP0)

Channel B (B)

Channel A (A)

Capture/Display

Buffer

(2560 Bytes)

Channel B uses only

the VP0D[19:10]

bidirectional pins

STCLK(C)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), and TSI (8-bit) capture modes.

Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-12. Video Port 0 Peripheral Signals

Device Overview

TMS320DM642 Datasheet(PDF) 26 Page - Texas Instruments

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