TMS320DM642 datasheet(94/178 Pages) TI

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5.8

External Memory Interface (EMIF)

5.8.1

EMIF Device-Specific Information

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

EMIF supports a glueless interface to a variety of external devices, including:

• Pipelined synchronous-burst SRAM (SBSRAM)

• Synchronous DRAM (SDRAM)

• Asynchronous devices, including SRAM, ROM, and FIFOs

• An external shared-memory device

EMIF Device Speed

The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets

the following requirements:

• 1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF

• up to 1 CE space of buffers connected to EMIF

• EMIF trace lengths between 1 and 3 inches

• 166-MHz SDRAM for 133-MHz operation

• 143-MHz SDRAM for 100-MHz operation

Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.

Verification of AC timings is mandatory when using configurations other than those specified above. TI

recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis application report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines

(see the Terminal Functions table for the EMIF output signals).

For more detailed information on the DM642 EMIF peripheral, see the TMS320C6000 DSP External

Memory Interface (EMIF) Reference Guide (literature number SPRU266).

DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 94 Page - Texas Instruments