TMS320DM642 datasheet(38/178 Pages) TI

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

VIDEO PORT 1 (VP1) OR McASP0 DATA OR McBSP1

VP1D[19]/AXR0[7](3)

AB12

VP1D[18]/AXR0[6](3)

AB11

VP1D[17]/AXR0[5](3)

AC11

VP1D[16]/AXR0[4](3)

AD11

VP1D[15]/AXR0[3](3)

AE11

VP1D[14]/AXR0[2](3)

AC10

VP1D[13]/AXR0[1](3)

AD10

Video port 1 (VP1) data input/output (I/O/Z) or McASP0 data pins (I/O/Z)

VP1D[12]/AXR0[0](3)

AC9

[default] and Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data

input/output (I/O/Z) [default]

VP1D[11]

AD9

By default, standalone VP1 data input/output pins have no function enabled

VP1D[10]

AE9

I/O/Z

IPD

upon reset. To configure these pins, see the Device Configuration section of this

VP1D[9]

AC8

data sheet.

VP1D[8]/CLKR1(3)

AD8

For more details on the McBSP1 pin functions or the McASP0 data pin functions,

VP1D[7]/FSR1(3)

AC7

see McBSP1 or McASP0 data sections of this table and the Device Configur-

ations section of this data sheet.

VP1D[6]/DR1(3)

AD7

VP1D[5]/CLKS1(3)

AE7

VP1D[4]/DX1(3)

AC6

VP1D[3]/FSX1(3)

AD6

VP1D[2]/CLKX1(3)

AE6

VP1D[1]

AF6

VP1D[0]

AF5

VP1CLK1

AF10

I/O/Z

IPD

VP1 clock 1 (I/O/Z)

VP1CLK0

AF8

IPD

VP1 clock 0 (I)

VP1CTL2

AD5

VP1 control 2 (I/O/Z)

VP1CTL1

AE5

I/O/Z

IPD

VP1 control 1 (I/O/Z)

VP1CTL0

AF4

VP1 control 0 (I/O/Z)

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