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TMS320DM642 Datasheet(PDF) 41 Page - Texas Instruments |
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TMS320DM642 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 178 page ![]() www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Table 2-4. Terminal Functions (continued) SIGNAL IPD/ TYPE(1) DESCRIPTION IPU(2) NAME NO. ETHERNET MAC (EMAC) HD31/AD31/MRCLK(3) G1 I Host-port data (I/O/Z) [default] or EMAC transmit/receive or control pins (I) (O/Z) HPI pin functions are default, see the Device Configurations section of this data HD30/AD30/MCRS(3) H3 I sheet. EMAC Media Independent I/F (MII) data, clocks, and control pins for HD29/AD29/MRXER(3) G2 I Transmit/Receive. • MII transmit clock (MTCLK), HD28/AD28/MRXDV(3) J4 I Transmit clock source from the attached PHY. HD27/AD27/MRXD3(3) H2 I • MII transmit data (MTXD[3:0]), HD26/AD26/MRXD2(3) J3 I Transmit data nibble synchronous with transmit clock (MTCLK). HD25/AD25/MRXD1(3) J1 I • MII transmit enable (MTXEN), HD24/AD24/MRXD0(3) K4 I This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]). HD22/AD22/MTCLK(3) L4 I • MII collision sense (MCOL) HD21/AD21/MCOL(3) K2 I Assertion of this signal during half-duplex operation indicates network HD20/AD20/MTXEN(3) L3 O/Z collision. HD19/AD19/MTXD3(3) L2 O/Z During full-duplex operation, transmission of new frames will not begin if this pin is asserted. HD18/AD18/MTXD2(3) M4 O/Z • MII carrier sense (MCRS) HD17/AD17/MTXD1(3) M2 O/Z Indicates a frame carrier signal is being received. • MII receive data (MRXD[3:0]), Receive data nibble synchronous with receive clock (MRCLK). • MII receive clock (MRCLK), Receive clock source from the attached PHY. HD16/AD16/MTXD0(3) M3 O/Z • MII receive data valid (MRXDV), This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]) and • MII receive error (MRXER), Indicates reception of a coding error on the receive data. Device Overview 41 |
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