TMS320DM642 datasheet(91/178 Pages) TI

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CLKIN

CLKOUT4

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 5-15. Timing Requirements for CLKIN for –720 Devices

(1) (2) (3) (see Figure 5-11)

–720

NO.

PLL MODE x12

PLL MODE x6

x1 (Bypass)

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(CLKIN)

Cycle time, CLKIN

16.6

33.3

13.3

33.3

13.3

33.3

tw(CLKINH)

Pulse duration, CLKIN high

0.45C

tw(CLKINL)

Pulse duration, CLKIN low

0.45C

tt(CLKIN)

Transition time, CLKIN

tJ(CLKIN)

Period jitter, CLKIN

0.02C

(1)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(2)

For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.

(3)

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

Figure 5-11. CLKIN Timing

Table 5-16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4

(1) (2) (3)

(see Figure 5-12)

–500

–600

–720

NO.

PARAMETER

UNIT

CLKMODE = x1, x6, x12

MIN

MAX

tw(CKO4H)

Pulse duration, CLKOUT4 high

2P – 0.7

2P + 0.7

tw(CKO4L)

Pulse duration, CLKOUT4 low

2P – 0.7

2P + 0.7

tt(CKO4)

Transition time, CLKOUT4

(1)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(2)

PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

(3)

P = 1/CPU clock frequency in nanoseconds (ns)

Figure 5-12. CLKOUT4 Timing

DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 91 Page - Texas Instruments

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