TMS320DM642 datasheet(124/178 Pages) TI

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5.11

Host-Port Interface (HPI)

5.11.1

HPI Peripheral Register Description(s)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

The HPI is a parallel port through which a host processor can directly access the CPU memory space.

The host device functions as a master to the interface, which increases ease of access. The host and

CPU can exchange information via internal or external memory. The host also has direct access to

memory-mapped peripherals. Connectivity to the CPU memory space is provided through the enhanced

DMA (EDMA) controller. Both the host and the CPU can access the HPI control register (HPIC) and the

HPI address register (HPIA). The host can access the HPI data register (HPID) and the HPIC by using the

external data and interface control signals.

For more detailed information on the HPI peripheral, see the TMS320C6000 DSP Host Port Interface

(HPI) Reference Guide (literature number SPRU578).

Table 5-38. HPI Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

–

HPID

HPI data register

Host read/write access only

0188 0000

HPIC

HPI control register

HPIC has both Host/CPU read/write access

HPIA

HPI address register

0188 0004

(HPIAW)(1)

(Write)

HPIA has both Host/CPU read/write access

HPIA

HPI address register

0188 0008

(HPIAR)(1)

(Read)

0188 000C – 0189 FFFF

–

Reserved

HPI transfer request control

018A 0000

HPI_TRCTL

018A 0004 – 018B FFFF

–

Reserved

(1)

Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR

independently.

124

DM642 Peripheral Information and Electrical Specifications

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