PM6344 datasheet(207/256 Pages) PMC

207 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

194

13.2 Using the Internal FDL Receiver

On power up of the EQUAD, the RFDL should be disabled by setting the EN bit

in the Configuration Register to logic 0. The RFDL Interrupt Control/Status

interrupt will be generated.

After the Interrupt Control/Status Register has been written to, the RFDL can be

enabled at any time by setting the EN bit in the Configuration Register to logic 1.

When the RFDL is enabled, it will assume that the link status is idle (all ones)

and immediately begin searching for flags. When the first flag is found, an

interrupt will be generated (if enabled), and the byte received before the first flag

was detected will be written into the FIFO buffer. Because the FLG and EOM

bits are passed through the buffer, this dummy write allows the RFDL Status

EOM as logic 1 and FLG as logic 1. The first interrupt and data byte read after

the RFDL is enabled (or TR bit set to logic 1) is an indication of the link status,

and the data byte should therefore be discarded. It is up to the controlling

processor to keep track of the link state as idle (all ones or bit-oriented

messages active) or active (flags received).

The RFDL can be used in a polled, interrupt driven, or DMA controlled mode for

the transfer of frame data.

Polled Mode

In the polled mode, the RDLINT[x] and RDLEOM[x] outputs of the RFDL are not

used, and the processor controlling the RFDL must periodically read the RFDL

Interrupt/Status to determine when to read the Data Register. If the RFDL data

transfer is operating in the polled mode, entry to the service routine is from a

timer. The processor service routine should process the data in the following

order:

1. Poll the INT bit in the RFDL Interrupt/Status Register until it is set to logic 1.

PM6344 Datasheet(PDF) 207 Page - PMC-Sierra, Inc