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PM6344 Datasheet(PDF) 209 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 209 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
196
c) If FLG=1 and the link state was inactive, then set the link state to active,
discard the last data byte, and go to step 1.
ELSE
d) Save the last data byte read.
e) If EOM=1, then read the CRC and NVB[2:0] bits of the RFDL Status
Register to process the frame properly.
f) If FE=0, then go to step 2, else go to step 1.
DMA-Controlled Mode
The RFDL can also be used with a DMA controller to process the frame data. In
the DMA controlled mode, the RDLINT[x] output of the RFDL is used as a DMA
request input to the DMA controller, and the RDLEOM[x] output is used as an
interrupt to the processor to allow handling of exceptions and as an indication of
when to process a frame. The RXDMASIG bit of the Datalink Options Register
should be set to logic 1.
The RDLINT[x] output of the RFDL is connected through a gate to the DMA
request input of the DMA controller to optionally inhibit the DMA request if the
RDLEOM[x] output is high. The DMA controller reads the data bytes from the
RFDL whenever the RDLINT[x] output is high. When the current byte read from
the Data Register is the last byte in a frame (due to an end-of-message or an
abort), or an overrun condition occurs, then the RDLEOM[x] output goes high.
The DMA controller is inhibited from reading any more bytes, and the processor
is interrupted. The processor can then halt the DMA controller, read the Status
Register, process the frame, and finally reset the DMA controller to process the
data for the next frame. The RDLEOM[x] output can optionally be enabled to
generate a processor interrupt through the common INTB output via the
RDLEOME bit in the Datalink Options register, rather than tying the RDLEOM[x]
output directly to the microprocessor. This allows a central microprocessor
controlling the EQUAD operation to also respond to conditions affecting the DMA
servicing of RFDL. When using the INTB output, the central processor must poll
the Interrupt ID/Clock Monitor, and the Interrupt Source Registers to identify the
source of the interrupt before beginning any interrupt service routine.



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