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PM6344 Datasheet(PDF) 222 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 222 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
209
The jitter on the recovered clock is absorbed by the two frame slip buffer in the
elastic store. BRPCM[x], BRSIG[x], and BRFPO[x] are updated on the falling
edge of RCLKO[x].
The framing alignment on BRPCM[x] and BRSIG[x] is still set by the BRFPI
input. However, BRFPI must now be timed with respect to the individual output
clock RCLKO[x] instead of BRCLK for each quadrant of the EQUAD in which
RCLKOSEL is set to logic 1. A possible configuration would have RCLKOSEL
set to logic 1 in only one quadrant and BRFPI timed to that quadrant's RCLKO.
The same RCLKO can then be connected to BRCLK which will be used as the
timing reference for all the other quadrants which will have RCLKOSEL set to
logic 0. Otherwise, if backplane frame alignment is not necessary, RCLKOSEL
can be set to logic 1 in every quadrant and BRFPI should be tied low.
Figure 31 shows the functional waveforms for a configuration where RCLKOSEL
is set to logic 1 in quadrant x. BRFPI and all the backplane outputs are timed to
RCLKO[x].
Figure 31
- Receive Backplane Interface with RCLKOSEL = 1
1 2 345 6 7 8
AB C D
1 2 3 456 78 1 23 4 5 67 8
AB C D
1 23 4 5 67 8 1 2 345 6 7 8
AB C D
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 16
Timeslot 17
RCLKO[x]
BRFPO[x]
BRPCM[x]
BRSIG[x]
BRFPI
Undefined
Undefined
Undefined
It should also be noted that RFP[x] can no longer be sampled by RCLKO[x] since
RCLKO[x] is a smoothed version of the recovered clock, and RFP[x] is timed by
the unsmoothed recovered clock.
Register bits TRSLIP and ELSTBYP in the Receive Options register and
BRX2RAIL in the Receive Backplane Options register must be cleared to logic 0
for proper operation. The DJAT Configuration register should be cleared to all
zeros to disable the LIMIT and SYNC bits. Note that the DJAT PLL is no longer
in the transmit path. Therefore, the FIFOBYP bit of the Transmit Interface
Configuration register must be set. to logic 1.



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