PM6344 datasheet(219/256 Pages) PMC

219 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

206

5. If there is more data to be read, go back to step 1.

13.5 Using the Digital Jitter Attenuator

The key to using DJAT lies in selecting the appropriate divisors for the phase

comparison between the selected reference clock and the generated smooth

TCLKO.

13.5.1

Default Application

Upon reset, the EQUAD default condition provides jitter attenuation with

TCLKO[x] referenced to the transmit clock, BTCLK[x]. The DJAT SYNC bit is also

logic 1 by default. DJAT is configured to divide its input clock rate, BTCLK[x], and

its output clock rate, TCLKO[x], both by 48, which is the maximum length of the

FIFO. These divided down clock rates are then used by the phase comparator to

update the DJAT DPLL. The phase delay between BTCLK[x] and TCLKO[x] is

synchronized to the physical data delay through the FIFO. For example, if the

phase delay between BTCLK[x] and TCLKO[x] is 12UI, the FIFO will be forced to

lag its output data 12 bits from its input data.

The default mode works well with the transmit backplane running at 2.048MHz.

13.5.2

Data Burst Application

In applications where a higher transmit backplane rate with external gapping is

used, a few factors must be considered to adequately filter the resultant

TCLKO[x] into a smooth 2.048MHz clock. The magnitude of the phase shifts in

the incoming bursty data can be too large to be properly attenuated by the PLL

alone. However, the magnitudes, and the frequency components of these phase

shifts are known, and are most often multiples of 8 kHz.

When using a gapped higher rate clock, the phase shifts of the input clock with

respect to the generated TCLKO[x] in this case can be large, but when viewed

over a longer period, such as a frame, there is little net phase shift. Therefore, by

choosing the divisors appropriately, the large phase shifts can be filtered out,

leaving a stable reference for the DPLL to lock onto. In this application, the N1

and N2 divisors should be changed to FFH (i.e. divisors of 256). Consequently,

the frequency of the clock inputs to the phase discriminator in the PLL is 8 kHz.

The DJAT SYNC option must be disabled, since the divisor magnitude of 256 is

not an integer multiple of the FIFO length, 48.

The self-centering circuitry of the FIFO should be enabled by setting the CENT

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