PM6344 datasheet(220/256 Pages) PMC

220 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

207

end of the FIFO registers, and then disengages. Should variations in the

frequency of input clock or the output clock cause the read pointer to drift to

within one unit interval of FIFO overflow or underflow, the pointer will be

incrementally pushed away by the LIMIT control without any loss of data.

With SYNC disabled, CENT and LIMIT enabled, the maximum tolerable phase

difference between the bursty input clock and the smooth TCLKO is 40UI. Phase

wander between the two clock signals is compensated for by the LIMIT control.

13.5.3

Elastic Store Application

In multiplex applications where the jitter attenuation is not required, the DJAT

FIFO can be used to provide an elastic store function. For example, in a M12

application, the data is written into the FIFO at 2.048MHz and the data is read

out of the FIFO with a gapped E2 rate clock applied on TCLKI[x]. In this

configuration, the Timing Options OCLKSEL[1:0] bits should be programmed to

01, the TCLKISEL bit should be programmed to 1, and the SMCLKO bit should

be programmed to 1. Also, the DJAT SYNC and LIMIT bits should be disabled

and the CENT bit enabled. This provides the maximum phase difference

between the input clock and the gapped output clock of 40UI. The maximum jitter

and wander between the two clocks is 8UIpp.

13.5.4

Alternate TCLKO Reference Application

In applications where TCLKO[x] is referenced to an Nx8 kHz clock source applied

on TCLKI[x], DJAT can be configured by programming the output clock divisor,

N2, to FFH and the input clock divisor, N1, to the value (N-1). The resultant input

clocks to the phase comparator are both 8kHz. The DJAT SYNC and LIMIT bits

should be disabled in this configuration.

PM6344 Datasheet(PDF) 220 Page - PMC-Sierra, Inc