PM6344 datasheet(218/256 Pages) PMC

218 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

205

13.4.2

Direct Access Mode

Direct access mode to the TPSC is not used in the EQUAD. However, direct

access mode is selected by default whenever the EQUAD is reset. The IND bit

within the TPSC Configuration Register must be set to logic 1 after a reset is

applied.

13.4.3

Indirect Access Mode

Indirect access mode is selected by setting the IND bit in the TPSC Configuration

BUSY indication bit should be polled to determine the status of the

microprocessor access: when the BUSY bit is logic 1, the TPSC is processing an

access request; when the BUSY bit is logic 0, the TPSC has completed the

request.

The indirect write programming sequence for the TPSC is as follows:

1. Check that the BUSY bit in the TPSC µP Access Status Register is logic 0.

2. Write the timeslot data to the TPSC Timeslot Indirect Data Buffer register.

3. Write RWB=0 and the timeslot address to the TPSC Timeslot Indirect

Address/Control Register.

4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1

immediately after step 3 and remain at logic 1 until the request is complete.

5. If there is more data to be written, go back to step 1.

The indirect read programming sequence for the TPSC is as follows:

1. Check that the BUSY bit in the TPSC µP Access Status Register is logic 0.

2. Write RWB=1 and the timeslot address to the TPSC Timeslot Indirect

Address/Control Register.

3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to

logic 1 immediately after step 2 and remain at logic 1 until the request is

complete.

4. Read the requested timeslot data from the TPSC Timeslot Indirect Data

Buffer register.

PM6344 Datasheet(PDF) 218 Page - PMC-Sierra, Inc