PM6344 datasheet(215/256 Pages) PMC

215 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

202

13.3.1

Payload Loopback

When PAYLOAD loopback (PAYLB) is initiated by writing 20H to the Master

Diagnostics Register (00AH) and disabling the TPSC by clearing the PCCE bit in

the TPSC Configuration Register (030H) to 0, the framer is configured to

internally connect the output of the ELST to the PCM input of TRAN. Payload

loopback will only function if there is a valid BTCLK input signal and a valid

BTFP signal (alternatively, BTFP can be tied either high or low). BTFP cannot,

though, be derived from the BRFPO output of the loopbacked channel. The data

is read out of ELST timed to the transmitter clock, and the transmit frame

alignment indication is used to synchronize the output frame alignment of ELST.

Note that the BTSIG[x] stream is still presented to the TRAN; therefore, the

SIGEN and DLEN bits of the TRAN Configuration register should be cleared to

logic 0 if the signaling is to be looped back. The BTSIG[x], BTCLK[x] and

BTFP[x] signals must be active during payload loopback. Conceptually, the data

flow through a single E1 framer in this loopback condition can be shown as

follows:

Figure 28

- Payload Loopback

DTIF

DJAT

TRAN

CDRC

FRMR

ELST

BTSIG[x]

BTPCM[x]

BTCLK[x]

BRFPI

BRCLK

BTFP[x]

BRPCM[x]

AIS

RDP/RDD[x]

RCLKI[x]

RDN/RLCV[x]

TDP/TDD[x]

TCLKO[x]

TDN/TFLG[x]

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