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PM6344 Datasheet(PDF) 112 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 112 Page - PMC-Sierra, Inc |
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112 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 99 Register 018H, 098H, 118H, 198H: DJAT Interrupt Status Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 Unused X Bit 1 R OVRI 0 Bit 0 R UNDI 0 This register contains the indication of the DJAT FIFO status. OVRI: The OVRI bit is asserted when an attempt is made to write data into the FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. UNDI: The UNDI bit is asserted when an attempt is made to read data from the FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. |
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