PM6344 datasheet(114/256 Pages) PMC

114 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

101

Bit

Type

Function

Default

Bit 7

R/W

N2[7]

Bit 6

R/W

N2[6]

Bit 5

R/W

N2[5]

Bit 4

R/W

N2[4]

Bit 3

R/W

N2[3]

Bit 2

R/W

N2[2]

Bit 1

R/W

N2[1]

Bit 0

R/W

N2[0]

This register defines an 8-bit binary number, N2, which is one less than the

magnitude of the divisor used to scale down the DJAT smooth output clock

signal. The output clock divisor magnitude, (N2+1), is the ratio between the

frequency of the smooth output clock and the frequency applied to the phase

discriminator input.

Writing to this register will reset the PLL and, if the SYNC bit is high, will also

reset the FIFO.

Upon reset of the EQUAD, the default value of N2 is set to decimal 47 (2FH).

Consult the Operations section for clarification of divisor selection criteria.

PM6344 Datasheet(PDF) 114 Page - PMC-Sierra, Inc

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