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PM6344 Datasheet(PDF) 118 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 118 Page - PMC-Sierra, Inc |
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118 / 256 page ![]() STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 105 Register 01DH, 09DH, 11DH, 19DH: ELST Interrupt Status Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 R/W SLIPE 0 Bit 1 R SLIPD X Bit 0 R SLIPI X SLIPE: The SLIPE bit position is an interrupt enable that when set, allows the INT output to go HIGH when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the Interrupt Status Register is read and the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full. If the Interrupt Status Register is read and the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty. SLIPI: The SLIPI bit is set if a slip occurred since the last read of the Interrupt Status register. The SLIPI bit is cleared just after the Interrupt Status register read operation. |
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