PM6344 datasheet(121/256 Pages) PMC

121 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

108

is checked again in the subsequent frames before checking the next bit

position for frame alignment.

CHKSEQ:

The CHKSEQ bit enables the use of the check sequence to verify the correct

frame alignment in the presence of random imitative frame alignment signals.

A logic 1 in the CHKSEQ bit position enables the use of the check sequence

algorithm in addition to the basic frame find algorithms; a logic 0 disables the

use of the check sequence algorithm.

CASA:

The CASA bit selects one of the two algorithms used to find Channel

Associated Signaling multiframe alignment. A logic 0 in the CASA bit position

selects the G.732-compatible algorithm; a logic 1 selects the alternate

framing algorithm.

REFR:

A transition from logic 0 to logic 1 in the REFR bit position forces the re-

synchronization to a new frame alignment. The bit must be cleared to logic 0,

then set to logic 1 again to generate subsequent re-synchronizations.

REFCRCE:

The REFCRCE bit enables excessive CRC errors (• 915 errors in one

second) to force a re-synchronization to a new frame alignment. Setting the

REFCRCE bit position to logic 1 enables reframe due to excessive CRC

errors; setting the REFCRCE bit to logic 0 disables CRC errors from causing

a reframe.

REFRDIS:

The REFRDIS bit disables reframing under any error condition once frame

alignment has been found; reframing can be initiated by software via the

REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain

"locked in frame" once initial frame alignment has been found. A logic 0

allows reframing to occur based on the various error criteria (FER, excessive

CRC errors, etc.). Note that while the FRMR remains locked in frame due to

REFRDIS=1, a received AIS will not be detected since the FRMR must be

out-of-frame to detect AIS.

PM6344 Datasheet(PDF) 121 Page - PMC-Sierra, Inc