 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PM6344 Datasheet(PDF) 119 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM6344 Datasheet(HTML) 119 Page - PMC-Sierra, Inc |
|
|
119 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 106 Register 01EH, 09EH, 11EH, 19EH: ELST Idle Code Bit Type Function Default Bit 7 R/W D7 1 Bit 6 R/W D6 1 Bit 5 R/W D5 1 Bit 4 R/W D4 1 Bit 3 R/W D3 1 Bit 2 R/W D2 1 Bit 1 R/W D1 1 Bit 0 R/W D0 1 The contents of the IDLE CODE register replace the timeslot data in the BRPCM serial data stream when the E1 framer is out of frame and the TRKEN bit in the Receive Options register is a logic 1. Since the transmission of all ones timeslot data is a common requirement, the IDLE CODE register is set to all ones on a reset condition. Bit 7 is the first to be transmitted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
