PM6344 datasheet(122/256 Pages) PMC

122 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

109

Bit

Type

Function

Default

Bit 7

R/W

FASC

Bit 6

R/W

BIT2C

Bit 5

R/W

SMFASC

Bit 4

R/W

T16C

Bit 3

R/W

RADEB

Bit 2

R/W

RMADEB

Bit 1

CMFACT

Bit 0

EXCRCE

FASC:

The FASC bit selects the criterion used to declare loss of frame alignment

signal: a logic 0 in the FASC bit position enables declaration of loss of frame

alignment when 3 consecutive frame alignment patterns have been received

in error; a logic 1 in the FASC bit position enables declaration of loss of frame

when 4 consecutive frame alignment pattern errors are detected.

BIT2C:

The BIT2C bit enables the additional criterion that loss of frame is declared

when bit 2 in time slot 0 of NFAS frames has been received in error on 3

consecutive occasions: a logic 1 in the BIT2C position enables declaration of

loss of frame alignment when bit 2 is received in error; a logic 0 in BIT2C

enables declaration of loss of frame alignment based on the setting of FASC,

only.

SMFASC:

The SMFASC bit selects the criterion used to declare loss of signaling

multiframe alignment signal: a logic 0 in the SMFASC bit position enables

declaration of loss of signaling multiframe alignment when 2 consecutive

multiframe alignment patterns have been received in error; a logic 1 in the

SMFASC bit position enables declaration of loss of signaling multiframe when

2 consecutive multiframe alignment patterns have been received in error or

when time slot 16 contains logic 0 in all bit positions for 1 or 2 multiframes

based on the criterion selected by T16C.

PM6344 Datasheet(PDF) 122 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 122 Page - PMC-Sierra, Inc

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