PM6344 datasheet(115/256 Pages) PMC

115 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

102

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

Reserved

Bit 4

R/W

CENT

Bit 3

R/W

UNDE

Bit 2

R/W

OVRE

Bit 1

R/W

SYNC

Bit 0

R/W

LIMIT

This register controls the operation of the DJAT FIFO read and write pointers and

controls the generation of interrupt by the FIFO status.

Reserved:

This bit should be written to a logic 1 for proper operation.

CENT:

The CENT bit allows the FIFO to self-center its read pointer, maintaining the

pointer at least 4 UI away from the FIFO being empty or full. When CENT is

set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data

bit period, and for the first 384 bit periods following an overrun or underrun

event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the

period will be extended by the number of UI that the EMPTY or FULL alarm

persists. During the EMPTY or FULL alarm conditions, data is lost. When

CENT is set to logic 0, the self-centering function is disabled, allowing the

data to pass through uncorrupted during EMPTY or FULL alarm conditions.

The SYNC bit must be set to logic 0 in order to set the CENT bit to logic 1.

OVRE,UNDE:

The OVRE and UNDE bits control the generation of an interrupt on the

microprocessor INTB pin when a FIFO error event occurs. When OVRE or

UNDE is set to logic 1, an overrun event or underrun event, respectively, is

allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is

set to logic 0, the FIFO error events are disabled from generating an interrupt.

PM6344 Datasheet(PDF) 115 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 115 Page - PMC-Sierra, Inc

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