PM6344 datasheet(113/256 Pages) PMC

113 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

100

Control

Bit

Type

Function

Default

Bit 7

R/W

N1[7]

Bit 6

R/W

N1[6]

Bit 5

R/W

N1[5]

Bit 4

R/W

N1[4]

Bit 3

R/W

N1[3]

Bit 2

R/W

N1[2]

Bit 1

R/W

N1[1]

Bit 0

R/W

N1[0]

This register defines an 8-bit binary number, N1, which is one less than the

magnitude of the divisor used to scale down the DJAT PLL reference clock input.

The REF divisor magnitude, (N1+1), is the ratio between the frequency of REF

input and the frequency applied to the phase discriminator input.

Writing to this register will reset the PLL and, if the SYNC bit in the DJAT

Configuration register is high, will also reset the FIFO.

Upon reset of the EQUAD, the default value of N1 is set to decimal 47 (2FH).

Consult the Operations section for clarification of divisor selection criteria.

PM6344 Datasheet(PDF) 113 Page - PMC-Sierra, Inc

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