 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PM6344 Datasheet(PDF) 117 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM6344 Datasheet(HTML) 117 Page - PMC-Sierra, Inc |
|
|
117 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 104 Register 01CH, 09CH, 11CH, 19CH: ELST Configuration Bit Type Function Default Bit 7 R/W ACCEL 0 Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 Unused X Bit 1 R/W IR 1 Bit 0 R/W OR 1 This register controls the format of the expected input frame to the ELST block and the format of the generated output frame from the ELST block. ACCEL: The ACCEL bit is used for production test purposes only. THE ACCEL BIT MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION. IR: The IR bit selects the input frame format. The IR bit must be set to logic 1 to properly handle the E1 frame format being input into the ELST. SETTING IR TO LOGIC 0 IS A RESERVED SETTING AND SHOULD NOT BE USED. OR: The OR bit selects the output frame format. The OR bit must be set to logic 1 to properly generate the E1 frame format output from the ELST. SETTING OR TO LOGIC 0 IS A RESERVED SETTING AND SHOULD NOT BE USED. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
