DS21352 datasheet(71/137 Pages) DALLAS

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DS21352/DS21552

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RPE

HSR.6

Receive Packet End. Set when the HDLC controller detects either the finish of a valid

message (i.e., CRC check complete) or when the controller has experienced a message

fault such as a CRC checking error, or an overrun condition, or an abort has been seen.

The setting of this bit prompts the user to read the RPRM register for details.

RPS

HSR.5

Receive Packet Start. Set when the HDLC controller detects an opening byte. The

setting of this bit prompts the user to read the RPRM register for details.

RHALF

HSR.4

Receive FIFO Half Full. Set when the receive 64–byte FIFO fills beyond the half way

point. The setting of this bit prompts the user to read the RPRM register for details.

RNE

HSR.3

Receive FIFO Not Empty. Set when the receive 64–byte FIFO has at least one byte

available for a read. The setting of this bit prompts the user to read the RPRM register

for details.

THALF

HSR.2

Transmit FIFO Half Empty. Set when the transmit 64–byte FIFO empties beyond the

half way point. The setting of this bit prompts the user to read the TPRM register for

details.

TNF

HSR.1

Transmit FIFO Not Full. Set when the transmit 64–byte FIFO has at least one byte

available. The setting of this bit prompts the user to read the TPRM register for details.

TMEND

HSR.0

Transmit Message End. Set when the transmit HDLC controller has finished sending a

message. The setting of this bit prompts the user to read the TPRM register for details.

NOTE:

The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.

DS21352 Datasheet(PDF) 71 Page - Dallas Semiconductor