DS21352 datasheet(83/137 Pages) DALLAS

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DS21352/DS21552

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16. LINE INTERFACE FUNCTION

The line interface function in the DS21352/552 contains three sections; (1) the receiver which handles

clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter

attenuator. Each of the these three sections is controlled by the Line Inter-face Control Register (LICR)

which is described below.

LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)

(MSB)

(LSB)

EGL

JAS

JABDS

DJA

TPD

SYMBOL

POSITION

NAME AND DESCRIPTION

LICR.7

Line Build Out Select Bit 2. Sets the transmitter build out; see Table 16-1

LICR.6

Line Build Out Select Bit 1. Sets the transmitter build out; see Table 16-1

LICR.5

Line Build Out Select Bit 0. Sets the transmitter build out; see Table 16-1

EGL

LICR.4

Receive Equalizer Gain Limit. 0 = –36 dB 1 = –30 dB

JAS

LICR.3

Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place

the jitter attenuator on the transmit side

JABDS

LICR.2

Jitter Attenuator Buffer Depth Select 0 = 128 bits 1 = 32 bits (use for delay

sensitive applications)

DJA

LICR.1

Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled

TPD

LICR.0

Transmit Power Down. 0 = normal transmitter operation 1 = powers down the

transmitter and 3-states the TTIP and TRING pins

16.1 RECEIVE CLOCK AND DATA RECOVERY

The DS21352/552 contains a digital clock recovery system. See Figure 3-1 and Figure 16-1 for more

details. The DS21352/552 couples to the receive T1 twisted pair via a 1:1 transformer. See for details.

The 1.544 MHz clock applied to the MCLK pin is internally multiplied by 16 via an internal PLL and fed

to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16

times oversampler which is used to recover the clock and data. This oversampling technique offers

outstanding jitter tolerance (see Figure 16-4).

Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS

waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,

a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock

applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the

RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly oversampled

digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most

applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the

Receive AC Timing Characteristics in section 24 for more details.

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