DS21352 datasheet(24/137 Pages) DALLAS

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DS21352/DS21552

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4.1.6 LINE INTERFACE PINS

Signal Name:

MCLK

Signal Description:

Master Clock Input

Signal Type:

Input

A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data

recovery and for jitter attenuation. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of the

TTL level clock source.

Signal Name:

XTALD

Signal Description:

Quartz Crystal Driver

Signal Type:

Output

A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK.

Leave open circuited if a TTL clock source is applied at MCLK.

Signal Name:

8XCLK

Signal Description:

Eight Times Clock

Signal Type:

Output

A 12.352 MHz clock that is locked to the 1.544 MHz clock provided from the clock/data recovery block (if the jitter attenuator

is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally

disabled by writing a 08h to TEST2.3 if not needed.

Signal Name:

LIUC

Signal Description:

Line Interface Connect

Signal Type:

Input

Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the

TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/ RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter

circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the

TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.

Signal Name:

RTIP & RRING

Signal Description:

Receive Tip and Ring

Signal Type:

Input

Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 16 for details.

Signal Name:

TTIP & TRING

Signal Description:

Transmit Tip and Ring

Signal Type:

Output

Analog line driver outputs. These pins connect via a transformer to the T1 line. See Section 16 for details.

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