ZLP32300 datasheet(22/99 Pages) ZILOG

22 / 99 page

Crimzon® ZLP32300

Product Specification

PS020823-0208

Pin Description

Comparator Inputs

In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference

is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its correspond-

ing IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as displayed in

Figure 10 on page 15. In DIGITAL mode, P33 is used as D3 of the Port 3 input register,

which then generates IRQ1.

Comparators are powered down by entering STOP mode. For P31–P33 to be used in a

Stop Mode Recovery source, these inputs must be placed into DIGITAL mode.

Comparator Outputs

These channels can be programmed to be output on P34 and P37 through the PCON regis-

ter.

RESET (Input, Active Low)

Reset initializes the MCU and is accomplished either through Power-On, Watchdog

Timer, Stop Mode Recovery, Low-Voltage detection, or external reset. During Power-On

Reset and Watchdog Timer Reset, the internally generated reset drives the reset pin Low

for the POR time. Any devices driving the external reset line must be open-drain to avoid

damage from a possible conflict during reset conditions. Pull-up is provided internally.

When the ZLP32300 asserts (Low) the RESET pin, the internal pull-up is disabled. The

ZLP32300 does not assert the RESET pin when under VBO.

The external Reset does not initiate an exit from STOP mode.

Note:

ZLP32300 Datasheet(PDF) 22 Page - Zilog, Inc.