ZLP32300 datasheet(53/99 Pages) ZILOG

53 / 99 page

Crimzon® ZLP32300

Product Specification

PS020823-0208

Functional Description

Stop Mode Recovery

Stop Mode Recovery Register (SMR)

This register selects the clock divide value and determines the mode of Stop Mode Recov-

ery (see Figure 31). All bits are write only except bit 7, which is read only. Bit 7 is a Flag

bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle.

Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 33 on

page 52) is required from the recovery source. Bit 5 controls the reset delay after recovery.

Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery

signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located

in Bank F of the Expanded Register Group at address 0Bh.

SMR(0F)0Bh

Figure 31. Stop Mode Recovery Register

SCLK/TCLK Divide-by-16

0 OFF * *

1 ON

Reserved (Must be 0)

Stop Mode Recovery Source

000 POR Only *

001 Reserved

010 P31

011 P32

100 P33

101 P27

110 P2 NOR 0-3

111 P2 NOR 0-7

Stop Delay

0 OFF

1 ON * * * *

Stop Recovery Level * * *

0 Low *

1 High

Stop Flag

0 POR *

1 Stop Recovery * *

*Default after Power-On Reset or Watchdog Reset

* *Default setting after Reset and Stop Mode Recovery.

* * *At the XOR gate input

* * * *Default setting after reset. Must be 1 if using a crystal or resonator clock source.

ZLP32300 Datasheet(PDF) 53 Page - Zilog, Inc.

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