ZLP32300 datasheet(35/99 Pages) ZILOG

35 / 99 page

Crimzon® ZLP32300

Product Specification

PS020823-0208

Functional Description

Initial_T8_Out/Rising_Edge

In TRANSMIT mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out-

put of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is

set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the

clock is enabled, a transition occurs to the initial state set by CTR1, D1.

In DEMODULATION mode, this bit is set to 1 when a rising edge is detected in the input

signal. In order to reset the mode, a 1 should be written to this location.

Initial_T16 Out/Falling _Edge

In TRANSMIT mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is

1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal

or PING-PONG mode (CTR1, D3; D2). When the counter is not enabled and this bit is set,

T16_OUT is set to the opposite state of this bit. This ensures that when the clock is

enabled, a transition occurs to the initial state set by CTR1, D0.

In DEMODULATION mode, this bit is set to 1 when a falling edge is detected in the input

signal. In order to reset it, a 1 should be written to this location.

Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output

from T8/16_OUT.

CTR2 Counter/Timer 16 Control Register—CTR2(D)02h

Table 9 lists and briefly describes the fields for this register.

Table 9. CTR2(D)02h: Counter/Timer16 Control Register

Field

Bit Position

Value

Description

T16_Enable

7-------

Counter Disabled

Counter Enabled

Stop Counter

Enable Counter

Single/Modulo-N

-6------

R/W

TRANSMIT Mode

Modulo-N

Single Pass

DEMODULATION Mode

T16 Recognizes Edge

T16 Does Not Recognize

Edge

Time_Out

--5-----

No Counter Timeout

Counter Timeout

Occurred

No Effect

Reset Flag to 0

Note:

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