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AD9891 Datasheet(PDF) 39 Page - Analog Devices |
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AD9891 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 58 page ![]() REV. A AD9891/AD9895 –39– VERTICAL TIMING EXAMPLE Figure 49 shows an example CCD timing chart for an interlaced readout. Each field can be broken down into four separate region areas. The vertical region change positions (RCPs) will set the line boundaries for each region area, and the region pointers will assign a unique region to each region area. Region Area 0 is a high speed vertical shift region. Sweep Mode can be used to generate this timing operation, with the desired number of high speed vertical pulses needed to “clean” the charge from the CCD’s vertical registers. Region Area 1 consists of only two lines and uses standard single line vertical shift timing. The timing of this region area will be the same as the timing in Region Area 3. Region Area 2 is the sensor gate line, where the VSG pulses trans- fer the image into the vertical CCD registers. This region will require the use of the second vertical sequence for SG lines. Region Area 3 also uses the standard single line vertical shift timing, the same timing as Region Area 1. In summary, three unique regions are required to support the four region areas, since Region Areas 1 and 3 use the same timing. Some of the timing parameters will need to be adjusted to read out the second field, such as the sensor gate pulse and line location. VD HD V1/VSG1 V2 V3/VSG2 V4 SUBCK MSHUT VSUB CCD OUT EXPOSURE PERIOD ( tEXP) INTERLACED READOUT PERIOD REGION AREA 1 REGION AREA 2 REGION AREA 0 REGION AREA 3 OPEN CLOSE OPEN Figure 49. Vertical Timing Example—Separate Regions |
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