AD9891 datasheet(33/58 Pages) AD

33 / 58 page

REV. A

AD9891/AD9895

–33–

PxGA GAIN REGISTER CODE

–2

–4

(100000)

(011111)

Figure 40. PxGA Gain Curve

VGA GAIN REGISTER CODE

1023

127

255

383

511

639

767

895

Figure 41. VGA Gain Curve (PxGA not included)

Variable Gain Amplifier

The VGA stage provides a gain range of 2 dB to 36 dB, pro-

grammable with 10-bit resolution through the serial digital

interface. Combined with approximately 4 dB from the PxGA

stage, the total gain range for the AD9891/AD9895 is 6 dB to

40 dB. The minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V. When com-

pared to 1 V full-scale systems (such as ADI’s AD9803), the

equivalent gain range is 0 dB to 34 dB.

The VGA gain curve follows a “linear-in-dB” characteristic.

The exact VGA gain can be calculated for any gain register

value by using the equation:

Gain

Code

=×

)

0 035

3 55

where the code range is 0 to 1023. PxGA default gain is included.

The gain accuracy specifications include the PxGA gain of

approximately 4 dB, for a total gain range of 6 dB to 40 dB.

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with a fixed

black level reference selected by the user in the Clamp Level

range between 0 LSB and 63.75 LSB in the AD9891 and be-

tween 0 LSB and 255 LSB in the AD9895. The resulting error

signal is filtered to reduce noise, and the correction value is

applied to the ADC input through a D/A converter. Normally,

the optical black clamp loop is turned on once per horizontal

line, but this loop can be updated more slowly to suit a particu-

lar application. If external digital clamping is used during

the post- processing, the AD9891/AD9895 optical black

clamping may be disabled using Bit D5 in the Operation Regis-

ter (see Serial Interface Timing and Register Listing sections).

When the loop is disabled, the Clamp Level Register may still

be used to provide programmable offset adjustment.

The optical black clamp is controlled by the CLPOB signal,

which is fully programmable (see Horizontal Clamping and

Blanking section). System timing examples are shown in the

Horizontal Timing Sequence Example section. The CLPOB

pulse should be placed during the CCD’s optical black pixels. It

is recommended that the CLPOB pulse duration be at least

20 pixels wide. Shorter pulsewidths may be used, but the ability

to track low frequency variations in the black level will be

reduced.

A/D Converter

The AD9891 uses a high a performance 10-bit ADC archi-

tecture, optimized for high speed and low power, while the

AD9895 uses a 12-bit ADC architecture. Differential

nonlinearity (DNL) performance is typically better than

0.5 LSB for both products. The ADC uses a 2 V input range.

Better noise performance results from using a larger ADC full-

scale range.

NOTES

1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “01230123” LINE.

2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “01230123” AND “23012301” LINES.

3. FLD STATUS IS IGNORED.

PxGA GAIN

FLD

ODD FIELD

EVEN FIELD

Figure 39g. 4-Color 2-Color Steering Mode

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