AD9891 datasheet(31/58 Pages) AD

31 / 58 page

REV. A

AD9891/AD9895

–31–

CCD: PROGRESSIVE BAYER

LINE0

GAIN0, GAIN1, GAIN0, GAIN1, ...

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

GAIN0, GAIN1, GAIN0, GAIN1, ...

MOSAIC SEPARATE COLOR

STEERING MODE

Figure 38a. CCD Color Filter Example: Progressive Scan

LINE0

GAIN0, GAIN1, GAIN0, GAIN1, ...

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1, ...

LINE0

GAIN2, GAIN3, GAIN2, GAIN3, ...

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

MOSAIC INTERLACED

COLOR STEERING MODE

EVEN FIELD

ODD FIELD

CCD: INTERLACED BAYER

Figure 38b. CCD Color Filter Example: Interlaced

NOTES

1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.

2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.

3. FLD STATUS IS IGNORED.

PxGA GAIN

FLD

ODD FIELD

EVEN FIELD

Figure 39a. Mosaic Separate Color Steering Mode

NOTES

1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.

2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323” LINE.

3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN).

PxGA GAIN

FLD

ODD FIELD

EVEN FIELD

Figure 39b. Mosaic Interlaced Color Steering Mode

example, the Mosaic Separate Steering Mode accommodates the

popular “Bayer” arrangement of Red, Green, and Blue filters

(see Figure 38a).

The same Bayer pattern can also be interlaced, and the Mosaic

Interlaced Mode should be used with this type of CCD (see

Figure 38b). The color steering performs the proper multiplex-

ing of the R, G, and B gain values (loaded into the PxGA gain

registers) and is synchronized by the vertical (VD) and horizon-

tal (HD) sync pulses. The PxGA gain for each of the four

channels is variable from –2dB to +10 dB, controlled in 64

steps through the serial interface. The PxGA gain curve is

shown in Figure 40.

COLOR

STEERING

CONTROL

4:1

MUX

PxGA

STEERING

MODE

SELECTION

PxGA GAIN

REGISTERS

CONTROL

BITS D0:D2

SHP/SHD

VGA

CDS

GAIN0

GAIN1

GAIN2

GAIN3

PxGA

Figure 37. PxGA Block Diagram

AD9891 Datasheet(PDF) 31 Page - Analog Devices

AD9891 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL