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PCI7510 Datasheet(PDF) 37 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 234 page  2–18 Table 2–14. CardBus PC Card Address and Data Terminals TERMINAL NAME NUMBER I/O DESCRIPTION NAME PDV GHK I/O DESCRIPTION CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 194 192 191 189 188 179 178 177 174 172 171 168 166 165 164 148 145 147 144 142 141 140 139 136 135 132 133 130 131 127 129 126 E08 C08 B08 E09 F09 F11 E11 C11 A12 C12 E12 C13 A14 E13 B14 F18 G17 F19 G18 H15 H14 H17 H18 J14 J17 K14 J19 K17 K15 L14 K18 L15 I/O CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit. CC/BE3 CC/BE2 CC/BE1 CC/BE0 176 163 149 137 B11 C14 G15 J15 I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24). CPAR 152 F14 I/O CardBus parity. In all CardBus read and write cycles, the PCI7510 device calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI7510 device outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the PCI7510 device compares its calculated parity to the parity indicator of the initiator; a compare error results in a parity error assertion. |
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