PCI7510 datasheet(63/234 Pages) TI

63 / 234 page

3–23

•

Cardbus bridge power management

•

ACPI support

TPS2211A or

TPS2221

Power Switch

PCI7510

PME

PC Card

Socket A

Smart Card

Socket

CLKRUN

PCI Bus

PRST

GRST†

Core Logic/

Embedded

Controller

1394

Socket

NCN6000

† The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI7510 device. PRST must be

asserted for subsequent warm resets.

Figure 3–14. System Diagram Implementing CardBus Device Class Power Management

3.9.1

1394 Power Management (Function 2)

The PCI7510 device complies with PCI Bus Power Management Interface Specification. The device supports the D0

(uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394

Open Host Controller Interface Specification, Appendix A.4 and PCI Bus Power Management Specification. PME is

supported to provide notification of wake events. Per Section A.4.2, the 1394 OHCI sets PMCSR.PME_STS in the

D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked interrupt events were

interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a specific interrupt event.

Based on feedback from Microsoft this implementation may cause problems with the existing Windows

power-management arcitecture as a PME and an interrupt could be simultaneously signaled on a transition from the

D1 to D0 state where interrupts were enabled to generate wake events. If bit 10 (ignore_mstrIntEna_for_pme) in the

PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.23) is set, then the PCI7510 device

implements the preferred behavior as (IntEvent.n && IntMask.n). Otherwise, the PCI7510 device implements the

preferred behavior as (IntEvent.n && IntMask.n && IntMask.masterIntEnable). In addition, when the

ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI vendor ID register (OHCI offset 40h, see

Section 8.15) to read 1, otherwise, bit 26 reads 0. An open drain buffer is used for PME.

3.9.2

Integrated Low-Dropout Voltage Regulator (LDO-VR)

The PCI7510 device requires 1.8-V core voltage. The core power can be supplied by the PCI7510 device itself using

the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the

VR_PORT terminal. Table 3–16 lists the requirements for both the internal core power supply and the external core

power supply.

Table 3–16. Requirements for Internal/External 1.8-V Core Power Supply

SUPPLY

VCC

VR_EN

VR_PORT

NOTE

Internal

3.3 V

GND

1.8-V output

Internal 1.8-V LDO-VR is enabled. A 1.0-

µF bypass capacitor is required on the VR_PORT

terminal for decoupling. This output is not for external use.

External

3.3 V

VCC

1.8-V input

Internal 1.8-V LDO-VR is disabled. An external 1.8-V power supply, of minimum 50-mA

capacity, is required. A 0.1-

µF bypass capacitor on the VR_PORT terminal is required.

PCI7510 Datasheet(PDF) 63 Page - Texas Instruments

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