PCI7510 datasheet(64/234 Pages) TI

64 / 234 page

3–24

3.9.3

CardBus (Function 0) Clock Run Protocol

The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI7510 device.

CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this

is not always available to the system designer, and alternate power-saving features are provided. For details on the

CLKRUN protocol see the PCI Mobile Design Guide.

The PCI7510 device does not permit the central resource to stop the PCI clock under any of the following conditions:

•

Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.30) is set.

•

The 16-bit PC Card resource manager is busy.

•

The PCI7510 CardBus master state machine is busy. A cycle may be in progress on CardBus.

•

The PCI7510 master is busy. There may be posted data from CardBus to PCI in the PCI7510 device.

•

Interrupts are pending.

•

The CardBus CCLK for the socket has not been stopped by the PCI7510 CCLKRUN manager.

•

Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.23) is set.

•

The 1394 resource manager is busy.

•

The PCI7610 1394 master state machine is busy. A cycle may be in progress on 1394.

•

The PCI7610 master is busy. There may be posted data from the 1394 bus to PCI in the PCI7610 device.

•

Interrupts are pending.

•

The 1394 bus is not idle.

The PCI7510 device restarts the PCI clock using the CLKRUN protocol under any of the following conditions:

•

A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.

•

A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket.

•

A CardBus attempts to start the CCLK using CCLKRUN.

•

A CardBus card arbitrates for the CardBus bus using CREQ.

•

A 1394 device changes the status of the twisted pair lines from idle to active.

3.9.4

CardBus PC Card Power Management

The PCI7510 device implements its own card power-management engine that can turn off the CCLK to a socket when

there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN

interface to control this clock management.

3.9.5

16-Bit PC Card Power Management

The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN

bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit

PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The

power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN

bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function

when there is no card activity.

NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and

PWRDWN modes.

3.9.6

Suspend Mode

The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global

reset) signal from the PCI7510 device. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the

PCI7510 device in order to minimize power consumption.

It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed

to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt

stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor

PCI7510 Datasheet(PDF) 64 Page - Texas Instruments

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