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PCI7510 Datasheet(PDF) 91 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 91 Page - Texas Instruments |
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91 / 234 page  4–18 4.30 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4–8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type RW RW RW RW R RW RW RW R RW RW RW RW RW RW RW Default 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type RW RW R R R R R R R RW RW RW RW R RW RW Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Register: System control Offset: 80h (Functions 0, 1) Type: Read-only, Read/Write Default: 0800 9060h Table 4–8. System Control Register Description BIT SIGNAL TYPE FUNCTION 31–30 ‡§ SER_STEP RW Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. 00 = INTA/INTB/INTC signal in INTA/INTB/INTC slots (default) 01 = INTA/INTB/INTC signal in INTB/INTC/INTD slots 10 = INTA/INTB/INTC signal in INTC/INTD/INTA slots 11 = INTA/INTB/INTC signal in INTD/INTA/INTB slots 29 ‡§ INTRTIE RW This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset 3Dh, see Section 4.25). This bit has no effect on INTC. 28 ‡ TIEALL RW This bit ties INTA, INTB, and INTC internally (to INTA), and reports this through the interrupt pin register (PCI offset 3Dh, see Section 4.25). 27 ‡ RSVD RW Internal oscillator is always enabled. 26 ‡§ SMIROUTE RW SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts are routed to IRQ2 (default). 1 = A CSC interrupt is generated on PC Card power changes. 25 ‡ SMISTATUS RW SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to this bit clears the status. 0 = SMI interrupt is signaled. 1 = SMI interrupt is not signaled. 24 ‡§ SMIENB RW SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled). 0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled. 23 RSVD R Reserved 22 ‡ CBRSVD RW CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low when a CardBus card has been inserted. When this bit is low, these signals are placed in a high-impedance state. 0 = Place the CardBus RSVD terminals in a high-impedance state. 1 = Drive the CardBus RSVD terminals low (default). ‡ One or more bits in this register are cleared only by the assertion of GRST. § These bits are global in nature and must be accessed only through function 0. |
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