PCI7510 datasheet(55/234 Pages) TI

55 / 234 page

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transition of SDA while SCL is in the high state, as shown in Figure 3–8. Data on SDA must remain stable during the

high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control

signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 3–8. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is

unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by

the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3–9

illustrates the acknowledge protocol.

SCL From

Master

123

SDA Output

By Transmitter

SDA Output

By Receiver

Figure 3–9. Serial-Bus Protocol Acknowledge

The PCI7510 device is a serial bus master; all other devices connected to the serial bus external to the PCI7510

device are slave devices. As the bus master, the PCI7510 device drives the SCL clock at nearly 100 kHz during bus

cycles and places SCL in a high-impedance state (zero frequency) during idle states.

Typically, the PCI7510 device masters byte reads and byte writes under software control. Doubleword reads are

performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software

control. See Section 3.7.4, Serial-Bus EEPROM Application, for details on how the PCI7510 device automatically

loads the subsystem identification and other register defaults through a serial-bus EEPROM.

Figure 3–10 illustrates a byte write. The PCI7510 device issues a start condition and sends the 7-bit slave device

address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave

device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI7510 device, then an

appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see Section 4.50). The word

address byte is then sent by the PCI7510 device, and another slave acknowledgment is expected. Then the PCI7510

device delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

PCI7510 Datasheet(PDF) 55 Page - Texas Instruments