PCI7510 datasheet(43/234 Pages) TI

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3–3

3.4

Clamping Voltages

The clamping voltages are set to match whatever external environment the PCI7510 device is interfaced with: 3.3 V

or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external

signals. The core power supply is 1.8 V and is independent of the clamping voltages. For example, PCI signaling can

be either 3.3 V or 5 V, and the PCI7510 device must reliably accommodate both voltage levels. This is accomplished

by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer

desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply.

3.5

Peripheral Component Interconnect (PCI) Interface

The PCI7510 device is fully compliant with the PCI Local Bus Specification. The PCI7510 device provides all required

signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by

connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI7510

device provides the optional interrupt signals INTA, INTB, and INTC for functions 0, 1, and 2, respectively.

3.5.1

1394 PCI Bus Master

As a bus master, the 1394 function of the PCI7510 device supports the memory commands specified in Table 3–1

below. The PCI master supports the memory read, memory read line, and memory read multiple commands. The

read command usage for read transactions of greater than two data phases are determined by the selection in bits

9–8 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For read

transactions of one or two data phases, a memory read command is used.

Table 3–1. PCI Bus Master Command Support

PCI

COMMAND

C/BE3–C/BE0

OHCI MASTER FUNCTION

Memory read

0110

DMA read from memory

Memory write

0111

DMA write to memory

Memory read multiple

1100

DMA read from memory

Memory read line

1110

DMA read from memory

Memory write and invalidate

1111

DMA write to memory

3.5.2

PCI Bus Lock (LOCK)

The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on

the PCI7510 device as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4

terminal by setting the appropriate values in bits 19–16 of the multifunction routing status register. See Section 4.36,

Multifunction Routing Status Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus

bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,

nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on

the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible

for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus

signal for this protocol is CBLOCK to avoid confusion with the bus clock.

An agent may need to do an exclusive operation because a critical access to memory might be broken into several

transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by

PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock

without interfering with nonexclusive real-time data transfer, such as video.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,

the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A

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