PCI7510 datasheet(44/234 Pages) TI

44 / 234 page

3–4

complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete

bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked

operation is in progress.

The PCI7510 device supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for

PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve

a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus

target supports delayed transactions and blocks access to the target until it completes a delayed read. This target

characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using

LOCK.

3.5.3

Serial EEPROM I2C Bus

The PCI7510 device offers many choices for modes of operation, and these choices are selected by programming

several configuration registers. For system board applications, these registers are normally programmed through the

BIOS routine. For add-in card and docking-station/port-replicator applications, the PCI7510 device provides a

two-wire inter-integrated circuit (IIC or I2C) serial bus for use with an external serial EEPROM.

The PCI7510 device is always the bus master, and the EEPROM is always the slave. Either device can drive the bus

low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the SCL

and SDA signal lines. The PCI7510 device is always the source of the clock signal, SCL.

System designers who wish to load register values with a serial EEPROM must use a pullup resistor on the SCL

terminal. If the PCI7510 device detects a logic-high level on the SCL terminal at the end of GRST, then it initiates

incremental reads from the external EEPROM. Any size serial EEPROM up to the I2C limit of 16 Kbits can be used,

but only the first 67 bytes (from offset 00h to offset 42h) are required to configure the PCI7510 device. Figure 3–3

shows a 2-Kbit serial EEPROM application.

In addition to loading configuration data from an EEPROM, the PCI7510 I2C bus can be used to read and write from

other I2C serial devices. A system designer can control the I2C bus, using the PCI7510 device as bus master, by

reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI

offset B3h, see Section 4.50) causes the PCI7510 device to route the SDA and SCL signals to the SDA and SCL

terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the

serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections

4.47, 4.48, and 4.49, respectively).

EEPROM interface status information is communicated through the serial bus control and status register (PCI offset

B3h, see Section 4.50). Bit 2 (EEDETECT) in this register indicates whether or not the PCI7510 serial ROM circuitry

detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 1

(DATAERR) being set. Bit 0 (EEBUSY) is set while the subsystem ID register is loading (serial ROM interface is busy).

The subsystem vendor ID for functions 2 and 3 is also loaded through SEEPROM. The SEEPROM load data goes

to all four functions from the serial EEPROM loader.

PCI7510 Datasheet(PDF) 44 Page - Texas Instruments