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PCI7510 Datasheet(PDF) 17 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 234 page  1–3 • Supports ring indicate, SUSPEND, and PCI CCLKRUN protocol and PCI bus Lock (LOCK) • Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals • Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394 • Compliant with Intel Mobile Power Guideline 2000 • Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume • Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down, ultralow-power sleep mode • Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s • Cable ports monitor line conditions for active connection to remote node • Cable power presence monitoring • Separate cable bias (TPBIAS) for each port • Physical write posting of up to three outstanding transactions • PCI burst transfers and deep FIFOs to tolerate large host latency • External cycle timer control for customized synchronization • Extended resume signaling for compatibility with legacy DV components • PHY-Link logic performs system initialization and arbitration functions • PHY-Link encode and decode functions included for data-strobe bit level encoding • PHY-Link incoming data resynchronized to local clock • Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s • Node power class information signaling for system power management • Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features • Isochronous receive dual-buffer mode • Out-of-order pipelining for asynchronous transmit requests • Register access fail interrupt when the PHY SCLK is not active • PCI power-management D0, D1, D2, and D3 power states • Initial bandwidth available and initial channels available registers • PME support per 1394 Open Host Controller Interface Specification • Advanced submicron, low-power CMOS technology 1.3 Related Documents • Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0) • 1394 Open Host Controller Interface Specification (Release 1.1) • IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995) • IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000) |
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