PCI7510 datasheet(89/234 Pages) TI

89 / 234 page

4–16

Table 4–7. Bridge Control Register Description (Continued)

BIT

SIGNAL

TYPE

FUNCTION

CPERREN

CardBus parity error response enable. This bit controls the response of the PCI7510 to CardBus parity

errors. This bit is separate for each socket.

0 = CardBus parity errors are ignored (default).

1 = CardBus parity errors are reported using CPERR.

4.27 Subsystem Vendor ID Register

The subsystem vendor ID register, used for system and option card identification purposes, may be required for

certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)

in the system control register (PCI offset 80h, See Section 4.30). When bit 5 is 0, this register is read/write; when bit

5 is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.

Bit

Name

Subsystem vendor ID

Type

Default

Subsystem vendor ID

Offset:

40h (Functions 0, 1)

Type:

Read-only, (Read/Write when bit 5 in the system control register is 0)

Default:

0000h

4.28 Subsystem ID Register

The subsystem ID register, used for system and option card identification purposes, may be required for certain

operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the

system control register (PCI offset 80h, see Section 4.30). When bit 5 is 0, this register is read/write; when bit 5 is

1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.

If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.

Bit

Name

Subsystem ID

Type

Default

Subsystem ID

Offset:

42h (Functions 0, 1)

Type:

Read-only, (Read/Write when bit 5 in the system control register is 0)

Default:

0000h

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