PCI7510 datasheet(77/234 Pages) TI

77 / 234 page

4–4

4.5

Command Register

The PCI command register provides control over the PCI7510 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification (see Table 4–3). None of the bit functions in this register are shared

among the PCI7510 PCI functions. Three command registers exist in the PCI7510 device, one for each function.

Software manipulates the PCI7510 functions as separate entities when enabling functionality through the command

functions, and these control bits appear to software to be separate for each function.

Bit

Name

Command

Type

Default

Command

Offset:

04h

Type:

Read-only, Read/Write

Default:

0000h

Table 4–3. Command Register Description

BIT

SIGNAL

TYPE

FUNCTION

15–11

RSVD

Reserved. Bits 15–11 return 0s when read.

INT_DISABLE

INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx assertion is enabled (default)

1 = INTx assertion is disabled

This bit is disabled (read-only 0) if bit 7 (PCI2_3_EN) in the general control register (PCI offset 86h, see

Section 4.31) is 0.

FBB_EN

Fast back-to-back enable. The PCI7510 device does not generate fast back-to-back transactions;

therefore, this bit is read-only. This bit returns a 0 when read.

SERR_EN

System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR

can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set

for the PCI7510 device to report address parity errors.

0 = Disables the SERR output driver (default)

1 = Enables the SERR output driver

RSVD

Reserved. Bit 7 returns 0 when read.

PERR_EN

Parity error response enable. This bit controls the PCI7510 response to parity errors through the PERR

signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by

asserting SERR.

0 = PCI7510 device ignores detected parity errors (default).

1 = PCI7510 device responds to detected parity errors.

VGA_EN

VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI7510 device does not respond

to palette register writes and snoops the data). When the bit is 0, the PCI7510 device treats all palette

accesses like all other accesses.

MWI_EN

Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory

write-and-invalidate commands. The PCI7510 controller does not support memory write-and-invalidate

commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns

0 when read. Writes to this bit have no effect.

SPECIAL

Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI7510

device does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns

0 when read. Writes to this bit have no effect.

MAST_EN

Bus master control. This bit controls whether or not the PCI7510 device can act as a PCI bus initiator

(master). The PCI7510 device can take control of the PCI bus only when this bit is set.

0 = Disables the PCI7510 ability to generate PCI bus accesses (default)

1 = Enables the PCI7510 ability to generate PCI bus accesses

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