CS5530A datasheet(237/259 Pages) AMD

237 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

237

Electrical Specifications

Revision 1.1

6.4.1

Definition of System Conditions for Measuring “On” Parameters

The current of the CS5530A is highly dependent on the DCLK (DOT clock). Table 6-5 shows how these factors are con-

trolled when measuring the typical average and absolute maximum CS5530A current parameters. Table 6-6 provides the

CS5530A’s core, DAC, and PLL DC characteristics during various power states.

Table 6-5. System Conditions Used to Determine CS5530A’s Current Used During the “On” State

CPU Current Measurement

System Conditions

VDD (Note 1)

See Table 6-3 on page 234 for nominal and maximum voltages.

DCLK Frequency (Note 2)

Not all system designs support display modes that require a DCLK of 157 MHz. Therefore, absolute maximum current

will not be realized in all system designs.

Typical Average

Nominal

50 MHz (Note 3)

A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a display image

of vertical stripes (4-pixel wide) alternating between black and white with power management disabled.

Absolute Maximum

Max

135 MHz (Note 4)

A DCLK frequency of 157 MHz is derived by setting the display mode to 1280x1024x8 bpp at 85 Hz, using a display

image of vertical stripes (1-pixel wide) alternating between black and white with power management disabled.

CS5530A Datasheet(PDF) 237 Page - Advanced Micro Devices