AS3900 datasheet(20/59 Pages) AMSCO

20 / 59 page

www.austriamicrosystems.com/RF-Transceivers/AS3900

Revision 1.00c

20 - 59

AS3900

Data Sheet - Detail ed Description

8.4.3 Reading of Data from Addressable Registers (READ Mode)

DATAI is sampled at the falling edge of SCLK, consequently, data to be read from the microcontroller are driven by the AS3900 (SDI slave) at the

transfer edge and sampled by the microcontroller (SDI master) at the sampling edge of SCLK.

An Enable LOW pulse has to be performed after register data has been transferred in order to indicate the end of the READ command and

prepare the Interface to the next command control Byte.

The command control Byte for a read command consists of a command code and an address. After the command code, the address of register

to be read has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred from the SDI slave to the master,

always from the MSB to the LSB. To transfer bytes from consecutive addresses, SDI master has to keep the SDI enable signal high and the SDI

clock has to be active as long as data need to be read from the slave.

Each bit of the command and address sections of the frame have to be driven by the SDI master on the SDI clock transfer edge and the SDI

slave samples it on the next SDI clock edge. Each bit of the data section of the frame has to be driven by the SDI slave on the SDI clock transfer

edge and the SDI master on the next SDI clock edge samples it. If the read access is interrupted (by de-asserting the SDI enable signal), data

provided to the master is consistent to given address, but it is only the register content from MSB to LSB. If more SDI clock cycles are provided,

the data remains consistent and each data byte belongs to the given or incremented address.

In the following figures two examples for a read command (without and with address self-increment) are given.

Figure 16. Reading of a Single Register Byte

Due to the limited range of the Register Address of 6 bits (A5 to A0) for reading a single Byte, only the register 0x00 to 0x3F are directly

addressable. All other registers (0x3F to 0x51 in the MAIN register) can only be accessed via the auto-incrementing Read cycle. The auto-

incrementing Read cycle can be applied by remaining SEN to HIGH and providing further clock cycles on SCLK (falling edges).

Figure 17. Reading of Register Data with Auto-incrementing Address

(

)

SE N

SC L K

SD AT AO

D a ta is m o v e d

from A ddres s

<A 5 -A 0 > + n

S E N fa llin g

edge signals

end of R E A D

M ode

D a ta is m o v e d

from A ddres s

<A 5 -A 0 > + (n -1 )

D a ta is m o v e d

from A ddres s

<A 5 -A 0 > + 1

D a ta is m o v e d

from A ddress

SD AT A I

01 patte rn indic a te s

R E A D M ode w ith

S tart A ddress

A < 5:0>

AS3900 Datasheet(PDF) 20 Page - ams AG

AS3900 Datasheet(HTML) 20 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL