AS3900 datasheet(37/59 Pages) AMSCO

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AS3900

Data Sheet - Detail ed Description

8.8.3 Frame structure for ACKNOWLEDGE with appended data (ACP)

This mode is used to send 4 bytes data (REG 0x2F, 0x30, 0x31, 0x32) from the Master to the Client. The transmission only takes place if the

data in these data registers is nonzero. The received data is stored in the same Client registers REG 0x2F, 0x30, 0x31, 0x32 and could be read

by the MCU.

After data was received successfully (correct ID and no CRC error) by the Master ACP will be send else NAK or NAP are send.

Table 33. Frame Structure

Preamble

ACP

data

CRC

8.8.4 Frame Structure for NOT-ACKNOWLEDGE (NAK)

After any data error at reception time window (incorrect ID and / or CRC error) NAK will be send.

Communication error counter will be increased. Communication will be terminated after communication error counter limit cesmax in REG

0x02<2:0> will be exceeded. The cesmax at the Master is the limit for all available Clients. The actual communication error count of each Client

is stored in SREG 0x14 to 0x17. If different communication error limits are requested for the different Clients, it is possible to offset the cesX

value for the separate Clients in SREG 0x14 to 0x17.

Table 34. Frame Structure

Preamble

NAK

8.8.5 Frame Structure for NOT-ACKNOWLEDGE and Data Retransmit (NAR)

After a CRC data error at reception time window (correct ID and CRC error) NAR will be send.

NAR error counter in REG 0x03<1:0> will be increased. After NAR error counter exceeds the maximum, NAK will be send and the

Communication counter is increased. After the client receives NAR, immediately the data is retransmitted and the client NAR error counter will be

increased.

Table 35. Frame Structure

Preamble

NAR

8.9 Configuration Registers

All configuration registers are readable and writable. The registers are arranged as addressable bytes. The configuration register settings do not

alter during Power down mode as long as the minimum supply voltage requirements are met. The bank bit at ADDRESS 0x00 bit<0> defines the

Main (bit value = 0) or the Shadow (bit value = 1) Register Bank.

8.9.1 Main Register Bank (ADDRESS 0x00 bit<0>=0)

16 bits

8bits

32 bits (REG 0x2F, 0x30, 0x31, 0x32)

16 bits

8bits

16 bits

8bits

Table 36. Main Register Bank (ADDRESS 0x00 bit<0>=0)

Address

0x00

ma_sen

osc32f

timdis

unidir

stream

wake_rx

pwr

bank

0x01

entm<7:0>

0x02

pretm<2:0>

reserved

cesmax<2:0>

0x03

reserved

longscan

reserved

osc27f

reserved

narmax<1:0>

0x04

fuseen

reserved

longwake_

wakecyc<2:0>

waketm<1:0>

0x05

mcs<1:0>

reserved

mcdr<3>

0x06

reserved

dev<2>

bitrate<1:0>

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