AS3900 datasheet(51/59 Pages) AMSCO

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AS3900

Data Sheet - Detail ed Description

8.10 Feature Description

This chapter describes how to apply certain features of the device.

8.10.1 One Time Programmable Memory (OTP)

The OTP is 4 times a 8bit (32bits) poly fuse based PROM. This is an austriamicrosystems IP-block called PPROM. It is described in a separate

documents P2PROM_rev1.322 and PPROM_appl_note_C.

The ID data has to be written into the Shadow Register Bank REG 0x08, 0x09, 0x0A.

8.10.1.1 Write to the OTP register

To enable the Write mode the device must be turned on with the command POWER_ON. Set the fuseen bit in REG 0x04<7> and switch to the

SHADOW register with the command SHADOW_BANK. The data (e.g. ID) that should be programmed must be written via SDI into the Shadow

Register Bank register dprom in REG 0x08 to 0x0A. These are already the physical PPROM registers, which are ready to be programmed.

8.10.1.2 Programming of the OTP

To enable the programming, the bit bank, REG 0x00<0>, bit fuseen, REG 0x04<7>, bit pwr, REG 0x00<1> and the bit osc27f, REG 0x03<4>

have to be set to 1. With the command PROM_FUSE pulse, the programming of the OTP is executed. After 2 ms the automatic fusing will be

ended. To verify the correct programming reset the chip by disconnecting the power supply of the AS3900. After powering the chip again, the

values read from the ID0 register must be the same as the programmed ones.

8.10.1.3 Read the Fuses

To enable the Read mode the bit bank, REG 0x00<0>, bit pwr, REG 0x00<1> and the bit osc27f, REG 0x03<4> must be set to 1. With the

command PROM_LOAD pulse the values of the fuses are loaded to the register dprom, REG 0x08 to 0x0A after 0.8ms. After reading the same

values are loaded to the ID0 register.

8.10.1.4 Read the Fuses and Load to ID0 Register

To enable this mode the bit bank, REG 0x00<0> must set 1. With the command PROM_COPY pulse the values of the fuses are loaded to the

register dprom, REG 0x08 to 0x0A and the values from the registers dprom are copied to the Main Register Bank register ID0, REG 0x08 to

0x0A.

The same procedure is performed with the POR Signal automatically.

0x15

reserved

[7]

R/W

Error Table

for Master

reserved

ces3<2:0>

[6:4]

Actual Communication Error count of 4

client

reserved

[3]

reserved

ces2<2:0>

[2:0]

Actual Communication Error count of 3

client

0x16

reserved

[7]

R/W

Error Table

for Master

reserved

ces5<2:0>

[6:4]

Actual Communication Error count of 6

client

reserved

[3]

reserved

ces4<2:0>

[2:0]

Actual Communication Error count of 5

client

0x17

reserved

[7]

R/W

Error Table

for Master

reserved

ces7<2:0>

[6:4]

Actual Communication Error count of 8

client

reserved

[3]

reserved

ces6<2:0>

[2:0]

Actual Communication Error count of 7

client

0x18 - 0x1D

reserved

[7:0]

reserved

Table 39. Shadow Register Bank (ADDRESS 0x00 bit<0>=1)

Name

Bit

Type

Description

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