AS3900 datasheet(43/59 Pages) AMSCO

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AS3900

Data Sheet - Detail ed Description

0x05

mcs<1:0>

[7:6]

R/W

Micro controller clock setting at pin MCU_CLK

OFF

32768 Hz

27MHz divided by mcdr<3:0> settings at active modes

27MHz divided by mcdr<3:0> settings at active modes, 32768

Hz between active modes

reserved

[5:4]

reserved

mcdr

[3:0]

Divider setting Micro controller clock at pin MCU_CLK (clock duty cycle 50%)

Clock source is the 27MHz crystal

0000

8 (8)

0001

12 (3*4)

0010

12 (3*4)

0011

18 (3*3*2)

0100

16 (16)

0101

24 (3*8)

0110

24 (3*8)

0111

36 (3*3*4)

1000

32 (32)

1001

48 (3*16)

1010

48 (3*16)

1011

72(3*3*8)

1100

64 (64)

1101

96 (3*32)

1110

96 (3*32)

1111

144 (3*3*16)

0x06

reserved

[7:3]

R/W

reserved

dev<2>

[2]

Select deviation frequency (setting for the nominal crystal frequency of

27.12MHz) for Master and Client

Deviation = ± 106 kHz

Deviation = ± 53 kHz

bitrate<1:0>

[1:0]

Transmission bitrate (setting for the nominal crystal frequency of 27.12MHz)

for Master and Client

26.5 kbit per sec

53 kbit per sec

106 kbit per sec

212 kbit per sec

Table 38. Main Register Bank (ADDRESS 0x00 bit<0>=0)

Address

Bit

Type

Description

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