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AS3900

Data Sheet - Detail ed Description

8.4.7 Microcontroller Clock Interface

The output frequency is derived from the 27MHz crystal oscillator. The division ratio is defined by register settings. To enable or disable the clock

output set the Clock Mode register bit. Additional different operation modes for the output could be set by Clock Mode register bits. For more

information on the operation modes of the clock output see Table 20. Clock Interface Modes.

Table 19. Clock Interface Electrical Description

Name

Signal

Signal Level

Description

Table 20. Clock Interface Modes

#

Mode

Mode (bit)

Clock Mode Description

CM7

CM6

Table 21. Clock Division Ratios

Division ratio

Pattern (com. bits)

Mode Description

mcdr[3]

mcdr[2]

mcdr[1]

mcdr[0]

Derived from 27.12MHz

MCU_CLK

Buffered Digital Output

CMOS

Buffered slope controlled clock output Maximum

Load = 50pF

1

MCUclk_Off

0

0

No clock is provided to pin MCU_CLK. Output Level is set to LOW.

2

MCUclk_32K

0

1

32kHz is always provided to pin MCU_CLK except in POWER DOWN

Mode

3

MCUclk_27M

1

0

A division ratio of 27MHz is provided to pin MCU_CLK in all active modes

except in SLEEP and POWER DOWN Mode. For division ratio (see Clock

Division Ratios)

4

MCUclk_32K/27M

1

1

In active modes (RX or TX active) a division ratio of 27MHz is provided to

pin MCU_CLK. In SLEEP Mode 32kHz is set. POWER DOWN Mode

switches off the MCU_CLK output.

8

000

0

3.39MHz

12

000

1

2.26MHz

12

001

0

2.26MHz

18

001

1

1.50MHz

16

010

0

1.69MHz

24

010

1

1.13MHz

24

011

0

1.13MHz

36

011

1

753kHz

32

100

0

847kHz

48

100

1

565kHz

48

101

0

565kHz

72

101

1

376kHz

64

110

0

423kHz

96

110

1

281kHz

96

111

0

281kHz

144

1

1

1

1

188kHz