VR4102 datasheet(322/701 Pages) NEC

322 / 701 page

CHAPTER 15 PMU (POWER MANAGEMENT UNIT)

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(2) Activation via GPIO Activation Interrupt

When the GPIO[12:9], GPIO[3..0] signal is asserted, the PMU checks the GPIO[12:9], GPIO[3..0]’s activation

interrupt enable bit. If GPIO[12:9], GPIO[3..0] activation interrupts are enabled, the PMU asserts the POWERON

signal and provides external notification that the CPU is being activated (since the GPIO[12:9], GPIO[2..0] activation

enable interrupt bit is cleared after an RTC is reset, the GPIO[12:9], GPIO[2..0] signal cannot be used for activation

immediately after an RTC reset. However, activation can occur at the falling edge of the GPIO[3] signal immediately

after an RTC reset for GPIO[3] only).

The PMU asserts the POWERON signal, then checks the BATTINH/

BATTINT# signal and de-asserts the POWERON signal.

When the BATTINH/BATTINT# signal is high (“1”), the PMU cancels peripheral unit reset, then starts the Cold

Reset sequence to activate the CPU core.

When the BATTINH/BATTINT# signal is low (“0”), the PMU sets “1” to PMUINTREG’s BATTINH bit and then

performs another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to “0”) by

software.

The CPU sets “1” to the corresponding GPIOINTR bit in the PMUINTREG regardless of whether activation

succeeds or fails.

Figure 15-3. Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 1)

BATTINH/

BATTINT#(i)

MPOWER(o)

POWERON(o)

GPIO[12:9]/

GPIO[3..0](i/o)

RTC(Internal)

Figure 15-4. Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 0)